An insulated gate field effect transistor has been developed, with installing a high-dielectric constant (high-k) film for a gate insulator film and a metal for a gate electrode. This type of transistor can reduce its gate-leak current and to keep the power consumption at a low level. The insulated gate field effect transistor according to the following method. That is, a dummy non-dielectric film is formed from a silicon oxide film on a silicon substrate and a dummy gate is formed thereon, and thereafter n-type impurities (or p-type impurities) are introduced into silicon substrates on both sides of the dummy gate to form a source/a drain. Further, after forming a sidewall of a silicon nitride film at both sides of the dummy gate, and via the step of removing the dummy gate and the dummy film in this order, and then both a high-dielectric constant gate insulator film and a metal gate electrode are formed.
In the above production process, there is, as an example, a method of using a diluted hydrofluoric acid in order to selectively remove the dummy film of the silicon oxide film after removing the dummy gate. However, in the wet etching of the dummy film using a diluted hydrofluoric acid, although selective etching is possible for the sidewall, a selective etching capacity for the source/drain is poor. As a result, a part of the source/drain exposed on the tip of the dummy gate under the sidewall is etched whereby a void (depression) is generated (for reference, e.g. Antoine Pacco et al., ECS Trans., Vol. 41, Issue 5, pp. 37-43) (for reference, void v in FIG. 2 attached). This is because a difference occurs between electrode potentials that materials have at the time of the wet etching on the ground that the impurity concentration of the source/drain is higher than the impurity concentration of a silicon substrate that becomes a channel-forming region between the source and the drain. Further, this is also because the source/drain and the channel-forming region become easy to undergo galvanic corrosion in combination with doping of impurities that are different in conductivity type from one another, and the end of the source/drain is dissolved with an etching liquid.
Also in a case of forming extension layers at gate ends of the source and the drain, the phenomenon similarly arises that the gate end sides of the extension layers are etched. This is because although the impurity concentration of the extension layer is lower than that of the source or the drain, there is a difference in the impurity concentration between the extension layer and the channel-forming region, and the conductivity type of the impurity is opposite to one another. When a void generates at the gate end side of the extension layer, a gate insulator film to be formed at the end of the extension layer is formed in the void in the case of forming a transistor. As a result, electric field gets centered on the portion, which gets to insulation breakdown. Thus, sometimes the transistor does not run.